(1) Field of the Invention
The present invention relates to the formation of planarized insulating layers on semiconductor substrates having high irregular surface features and more particularly, to the use of a two-step etch back spin-on-glass technique for planarizing a dielectric layer over a patterned conducting layer on the substrate.
(2) Description of the Prior Art
Today's Ultra Large Scale Integration (ULSI) on the semiconductor substrate are in part due to advances in photolithographic techniques and to advances in etching. For example, improvements in optical resolution and photoresist materials have lead to submicrometer resolution in photoresist image sizes. Likewise, the replacement of wet etching with directional plasma etching has resulted in submicrometer patterns being etched in the substrate and in the conducting and insulating layers which make up the integrated circuits on semiconducting substrates.
However, the accumulated effect of depositing these layers and the etching of patterns in these layers, one patterned layer on top of the other, has resulted in irregular or substantially nonplanar surface features on the otherwise microscopically planar substrate. This rough or irregular topography also results from other structures on the substrate. For example, stacked capacitors used in the dynamic random access memory (DRAM) extend up ward on the chip and adds to this roughness problem. This roughness is made substantially worse at later processing step where multilayer metallurgy is used to connect up the discrete devices for integrated circuits.
The advancements in down scaling of devices and the inter-connecting metal wiring have not come without certain technological problems. For example, the improvement in photolithographic resolution require a more shallow depth of focus during optical exposure of the photoresist. This results in unwanted distorted photoresist images over nonplanar portions of the substrates. Likewise, anisotropic etching to pattern the various conducting layers over the nonplanar surface can result in leaving unwanted portions of the conducting layer on the sidewalls of the underlying patterns which can lead to interlevel shorts. In addition, thinning of narrow inter-connecting metal lines over steps in underlying patterned layers can result in low yield and early failure of the circuit. This is especially true at high current densities where electromigration of the metal atoms in the metal lines can lead to voids and open lines, or can result in extrusion of metal between the closely spaced lines leading to shorts.
One approach of minimizing these topographic problems is to provide processes that preserve the planar nature of the substrate surface for receiving the next level of patterned layers. This planarization requirement is particularly important at the multilayer metallurgy levels, where the accumulative roughness of the surface topography can be quite severe.
Varies methods have been used for planarizing the dielectric layers that physically and electrically isolate these semiconductor devices and conducting metal layers. For example, some methods for forming planarized insulating layers over this rough topography include depositing bias sputtered silicon oxide, depositing and flowing of doped chemical vapor deposited (CVD) oxides, such as phosphosilicate glass (PSG) and borophosphosilicate glass (BPSG), biased plasma enhanced CVD (PECVD), and similar techniques. However, many of these techniques are time consuming and require costly process equipment.
More recently, new techniques using spin-on-glasses are finding increasing use for forming interlevel insulator that can be planarized. This type of glass is of particular interest because the deposition process and planarization is relatively simple and the process utilizes low cost equipment. For example, the insulating layer is deposited by spin coating a liquid precursor, similar to the spin application of photoresist. The layer is then dried to remove the solvents and baked on a hot plate or in a oven to cure the layer and to form an inorganic oxide by pyrolysis. The spin coating application of the liquid precursor composed of a solvent containing, for example, a silicate or siloxane polymer tend to fill in the recesses between the patterned metal areas being thicker than the coating over the metal area, thereby having a planarization effect on the resulting insulating over the patterned metal layer. Generally, several coatings are required to achieve a reasonable planarity. For example, D. L. Yen U.S. Pat. No. 5,003,062 describes a method for forming a multilayer metallurgy using a spin-on-glass layer as part of the planarized insulating layer.
Although these spin-on-glasses can be effective insulators for multilevel metallurgies, it is necessary to incorporate a barrier insulating layer, such as chemical vapor deposited (CVD) silicon oxide, to prevent the spin-on-glass from contacting and eroding the patterned metal layers, which are usually composed of aluminium. Furthermore, when via holes are formed in the CVD silicon oxide/spin-on-glass layers to contact the upper metal layer, it is necessary to carefully out gas the spin-on-glass exposed in the via hole so as to avoid the degradation of the metal therein.
An alternative approach is an etch back spin-on-glass process in which the cured spin-on-glass layer is blanket etched back leaving thicker isolated portions in the recessed areas between the patterned metal and removing the spin-on-glass down to the CVD silicon oxide barrier layer over the patterned metal thereby forming essentially a planar surface. Another CVD silicon oxide layer is then deposited over this planar structure and via holes are formed therein to provide contact for the upper metal layer formed thereon. Example of similar etch back process are shown by M. W. Batty U.S. Pat. No. 4,894,351 and by P. Merenda et al U.S. Pat. No. 4,826,786. Another example of filling the recess between a patterned metal layer with spin-on-glass is shown by I. S. Hyun et al U.S. Pat. No. 4,983,546.
Although out gassing is eliminated in the via holes because the spin-on-glass is removed from over the metal, a number of other problems can now occur that are associated with the etch back normally carried out in a plasma etcher. For example, when the spin-on-glass is etched back to the CVD silicon oxide, the ideal condition is to have an etch selectivity of 1:1, so as to maintain a planar surface as the exposed surface area of the spin-on-glass decreases and the surface area of underlying CVD silicon oxide increases. However, this is difficult to achieve because as the exposed surface of spin-on-glass rapidly decreases at the CVD silicon oxide surface, the available etchant species changes and results in an etch selectivity other than 1:1. This micro-loading effects is observed to be a significant problem when the spacing between patterned metal layer become less than about 0.8 micrometers.
Another problem which exasperates the etch back process is the occurrence of thinning of the spin-on-glass at the regions where there are significant steps in the underlying substrate. For example, one major concern is on substrates having dynamic random access memory (DRAM) chips, where the array of closely spaced stacked capacitors formed thereon extend substantially above the surface. When the spin-on-glass is etched back over the patterned metal layer near the edge, The exposed edge can result in interlevel short or other reliability problems.